Stacking Technique for Low Power SRAM
More details
Hide details
Publication date: 2019-11-23
Eurasian J Anal Chem 2018;13(3):em2018141
The static random access memory leakage current is becoming one of the critical concerns for low power devices. Double gate FinFET based SRAM became better choice for deep submicron technologies due to its better short channel effect. In this work, we review some of the leakage current sources and low power reduction technique to reduce leakage. As an improvement of our research work, 6T SRAM memory cells can be implemented using independent gate FinFET which gives lower leakage as well as better performance over the shorted gate FinFET mode. This is also implemented using stacking technique to decrease leakage. Therefore power consumed by the different SRAM cells are compared using Tanner tool in 45nm technology